There are numerous applications in which long shift registers are used to store digital data in a time-related fashion. Examples of such applications are the storage of single or multiple radar pulse trains for signal processing and the storage of television image data, especially computer graphics images. Shift register memory is also well suited to digital test equipment applications where an "instant replay" of events leading up to an anomalous condition is desired. Shift registers have the capability to accept binary data present at the input and duplicate that data at a later time at the output. Each bit of data entered moves one cell toward the output each time a clock pulse occurs. Contemporary shift registers have as many as 2048 cells in a single integrated circuit, and their relatively low cost per bit makes them an economical storage medium where random access to data is not required.
Conventional shift register memories are of two basic types, static and dynamic. The static type is clocked each time data appears, so that consecutive inputs always occupy consecutive cells. This provides storage efficiency through high density of data in the medium, but sacrifices all time-of-event information except sequence. Time information is sometimes encoded (counted) and stored along with the other data, necessitating additional storage capacity.
The dynamic type employs a clock pulse at a fixed rate such that the overall time for data to appear at the output is equal to the number of cells multiplied by the clock interval. The function of this type is similar to a delay line, except that there is an uncertainty in the delay time of plus or minus one clock interval, since data appearing between clock pulses is not entered until the next clock pulse occurs.
To illustrate the relative storage capacity required to mechanize either of the above types, an example of a storage requirement is given. Assume a series of events numbering up to 4096, each described by a 6-bit parallel binary data word which must be stored and retrieved along with time-of-event information having an accuracy of one microsecond within a 65,536-microsecond period of observation (recording). The static type shift register memory would require shift registers having a length of 4096 cells to accommodate 4096 events connected in a parallel-fed array to make each cell column capable of storing 22 bits of data (6 bits description and 16 bits time). The total static storage capacity required would thus be 22 .times. 4096 or 90,112 bits. The dynamic type would require only 6 bits parallel input capacity (for description) but to achieve the required time resolution, it would have to be clocked at a 1 MHz rate, necessitating a shift register length of 65,536 cells to cover the recording period. The total dynamic storage capacity required would therefore be 6 .times. 65,536, or 393,216 bits. This mechanization has very low storage efficiency, since over 65,000 cell columns are used to store a maximum of 4096 data words.